This was my thought as well. Any sufficiently complex modern CPU contains some register that it expects some bit to be set in to enable something like a powersaving mode with an interrupt mask in the lower bits to turn it off. Or something equally esoteric, but purposeful once you consider the application.
My recollection is that even the Atmega 8-bit microcontrollers have tons of special register groups around timers and interrupts.
Given the relative scarcity of "general purpose" registers on x86 32-bit CPUs, you could actually argue those are the special purpose registers.
> My recollection is that even the Atmega 8-bit microcontrollers have tons of special register groups around timers and interrupts.
Not precisely. AVR, like most embedded architectures, has a bunch of I/O registers which control CPU and peripheral behavior - but those are distinct from the CPU's general-purpose registers. The I/O registers exist in the same address space as main memory, and can only be accessed as memory. You can write an instruction like "increment general-purpose register R3", but you can't use that same syntax for e.g. "increment the UART baud rate register"; you have to load a value from that register to a GPR, increment it there, and store it back to the I/O register.
AVR is a bit weird in that the CPU's general-purpose registers are also mapped to main memory and can be accessed as if they were memory - but that functionality is rarely used in practice.
Getting back to your original point, x86 does have special-purpose registers - lots of them, in fact. They're accessed using the privileged rdmsr/wrmsr instructions.
My recollection is that even the Atmega 8-bit microcontrollers have tons of special register groups around timers and interrupts.
Given the relative scarcity of "general purpose" registers on x86 32-bit CPUs, you could actually argue those are the special purpose registers.