All PLL-based GPSDO designs that I've seen measure the difference between the rising edge of the 1PPS signal to the next rising edge of the 10MHz clock (or vice versa). You're basically using the kind of analog interpolation that's also used in frequency counters to get sub-10MHz clock cycle granularity. (See here: https://tomverbeure.github.io/2023/06/16/Frequency-Counting-...).
I understand that you can still implement a PLL with a pure digital 10ns counter (I've once designed one to create a 12.288MHz I2S clock out of a very jitters 48kHz audio sample tick), but I'm wondering what the benefits are of using the analog interpolator.
If the input 1PPS signal is so jittery, when do you get diminishing returns in increasing the precision of the pulse-to-pulse measurement?
I understand that you can still implement a PLL with a pure digital 10ns counter (I've once designed one to create a 12.288MHz I2S clock out of a very jitters 48kHz audio sample tick), but I'm wondering what the benefits are of using the analog interpolator.
If the input 1PPS signal is so jittery, when do you get diminishing returns in increasing the precision of the pulse-to-pulse measurement?