I disagree. FPGA design remains a highly-specialized area. Tools such as VivadoHLS, and other high-level synthesis tools, do provide some improvement in productivity though with inherent tradeoffs in design quality. There's been a lot of new hardware construction language popping up recently (e.g., HardCaml--which I happen to use, Chisel, Migen, PyMTL, etc.). They may bring something to the table in the coming years, but that's yet to be determined.

HardCaml's pretty great though, IMHO. But then again I'm already biased towards OCaml, and I get to work with its creator!