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Note that "100G optical connections" is physically implemented as "4x25G optical connections". The 4 wavelengths are coarsely spaced, which allows cheaper optical components to be employed. (As opposed to long-haul optics, where it is economical to squeeze many more wavelengths on the same fiber with costlier optics.)


I must say that I'm fascinated by the fact that each bit is around 1 cm long while in transit, at near the speed of light (in vacuum.)

Single channel 100 GB would mean 2-3 mm long bits. Imagine that :-)


Single channel 100GbE is already done, but not with OOK, it's coherent modulated qpsk, 16qam or 64qam single wavelength. But wider channel size in THz occupied than a single channel 1550 10GbE single wavelength OOK circuit.


And even 1cm at light speed is still a good 7 thousand cycles long at these frequencies.


Because it's 25 Gbps electrically per lane, this also allows for economies of scale with new 25 GbE optical and direct attach NICs for servers, where 10GbE is not enough, but 100 is too costly. There is some good documentation and reference links on 25GbE on Wikipedia for anyone who is curious. This also allows for one 100GbE top of rack switch port to be broken out into 4x25GbE individual connections.

So if you have a 1.5RU 32-port 100GbE top of rack switch it can serve up to 120 servers, leaving two 100GbE ports free for uplink.


The other issue that people miss here is the physical board that the switch ASIC is on. People might want to google SerDes and XAUI. The simplified bit here is back in the day first 10G you had 4 x 3.25G lanes. So for example for the Fulcrum FM4000 (24x10G) you had 64 traces on the board, 4 to each port. For something like the Broadcom Trident+ which could do 64 ports of 10G you have 256 traces. For each 10G there are 4 and they have to line up to the nm on the board unless you wanted to use a PHY and / or retimers. Arista shipped the 1st PHYless design of this. Less parts, higher MTBF, less heat and also less latency (phy add latency). To do 40G you would need 16 of the 3.25 (yuk). Things moved to 4x10G lanes and you got 40G ports. With the 25G Ethernet the lanes moved to 4x25G so you get 100G ports. Anyway random stuff if anyone is interested. Yes I know I am mixing the Serdes and XAUI stuff but this is a simpler view just talking about the lanes from the chip. Google will give great answers if you want to dig deeper.




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